Fire Emblem Gaiden
Type | single | Mapper | ? | Original mapper | 10 | PCB marks | 810428-C J256-61 | Tags: | | Uploaded: | 2022-11-26 01:10:32 |
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Elements:
Chip signature:
6264+27F080+27F080+74259+7430+7486+7402+AX5208C(VRC4)
PCB top:
PCB bottom:
Shell top:
Shell bottom:
No photo
Screenshoots:
No photo
Extra info:
Finally found bootleg Fire Emblem Gaiden from my [url=https://forums.nesdev.com/viewtopic.php?t=19364]wanted list[/url] - MMC4 port to VRC4. Unfortunately not in my posession, so gave my best to trace it basing on photos.
[url=https://obrazki.elektroda.pl/9748694000_1586035738.jpg][img]https://obrazki.elektroda.pl/9748694000_1586035738_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/8556648000_1586035741.jpg][img]https://obrazki.elektroda.pl/8556648000_1586035741_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/6672499800_1586035744.jpg][img]https://obrazki.elektroda.pl/6672499800_1586035744_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/1891616800_1586035746.png][img]https://obrazki.elektroda.pl/1891616800_1586035746_thumb.jpg[/img][/url]
[code]
74259 latches value of PPU-A5 to:
* LATCH0 (Q6) when PPU-A equals $0fd8..$0fdf or $0fe8..$0fef
dcba9876543210
$0fd8..$0fdf: 00111111011xxx
$0fe8..$0fef: 00111111101xxx
* LATCH1 (Q7) when PPU-A equals $1fd8..$1fdf or $1fe8..$1fef
dcba9876543210
$1fd8..$1fdf: 01111111011xxx
$1fe8..$1fef: 01111111101xxx
[/code]
VRC4 is wired as follows:
VRC4's PPU-A12 <= PPU-A12
VRC4's PPU-A11 <= ~((PPU-A12 | Q6) | ~(~PPU-A12 | Q7))
VRC4's PPU-A10 <= GND
VRC4's CPU_A12 <= ~(~CPU-A12 or /ROMSEL)
Mirroring is hard wired to V
Which, when PPU-A12=0, simplifies to:
VRC4 PPU-A12 <= 0
VRC4 PPU-A11 <= Q6
VRC4 PPU-A10 <= 0
When PPU-A12 = 1, simplifies to:
VRC4 PPU-A12 <= 1
VRC4 PPU-A11 <= Q7
VRC4 PPU-A10 <= 0
Which yields to the presence of following registers:
[code]
$9000 [...PPPP.] 8k PRG bank at $8000-$9fff
$9001 [...PPPP.] 8k PRG bank at $a000-$bfff
$B000 [....CC..] + $B001 [.....CCC], used when LATCH0=FD
$C000 [....CC..] + $C001 [.....CCC], used when LATCH0=FE
$D000 [....CC..] + $D001 [.....CCC], used when LATCH1=FD
$E000 [....CC..] + $E001 [.....CCC], used when LATCH1=FE
[/code]
This means that the original Fire Emblem Gaiden ROM needed to be changed - original registers were splited across two regs with bits shifted.
If they wired it a litle differently:
VRC-CPU-A0 <= 1
VRC-CHR-A14 <= CHR-ROM-A12
VRC-CHR-A15 <= CHR-ROM-A13
VRC-CHR-A16 <= CHR-ROM-A14
VRC-CHR-A17 <= CHR-ROM-A15
VRC-CHR-A18 <= CHR-ROM-A16
VRC-PRG-A12 <= PRG-ROM-A13
VRC-PRG-A13 <= PRG-ROM-A14
VRC-PRG-A14 <= PRG-ROM-A15
VRC-PRG-A15 <= PRG-ROM-A16
VRC-PRG-A16 <= PRG-ROM-A17
And forced, that for reads VRC-CPU-A13 need to be 1, otherwise CPU-A13, for example by the following circuit:
[code]
VRC-CPU-A13--+--<|----CPU-R/W
|
+---R----CPU-A13
[/code]
The original ROM could be run on this hardware without any ROM modifications!
Also no idea why - it does not affects anything:
VRC4's CPU_A12 <= ~(~CPU-A12 or /ROMSEL)
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