SMBJ2 ([mapper 40) a'ka 1990 Super Bros.4 - rev en
Finally got this rare SMB2J based on discrete chips (no PAL). It turned out to be [url=http://wiki.nesdev.com/w/index.php/INES_Mapper_040]mapper 40[/url]. I was wondering how did they wire all these chips to achieve that weird fixed banks. ([url=https://forums.nesdev.com/viewtopic.php?f=28&t=17108]I was able to do it using 2 chips less back in the days[/url]).
Funny how they used 2 NAND gates to make latch for IRQ assert/deassertion. And how the PRG/CHR address lines are shuffled.
PRG is identical to `Super Mario Bros. 4 (FDS Conversion)(Unl)[!]`, CHR differs in few bytes. And the difference is because of.. mario's outline:
[img]https://obrazki.elektroda.pl/2818807300_1580943774.png[/img]
[code]
$8000-$9fff: [........] - write acknowledges IRQs, clears and stop counter
$a000-$bfff: [........] - write starts counter (clocked by CPU cycles).
After 4096 cycles (~36 scanlines) IRQ is generated
$e000-$ffff: [.....PPP] - set prg bank
$6000 $8000 $a000 $c000 $e000
%110 %100 %101 PPP %111
Bus conflicts: no
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