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Cart name
Notes for chip search:
  • Use "+" as delimeter for all fields (except "cart name", where space is used); if many values are entered, all of them must appear in the cartridge then; case is not sensitive
  • "Mapper" is the actual mapper used by this cartridge hardware (might not match the one at wiki.nesdev.com, as at the moment I was analyzing this cartridge, there was no mapper assigned to it, so I had to assign my own number for testing)
  • "Original mapper" is the mapper used by licensed version of this game (for multicarts, it refers to mapper of the inside games, so 0+2 means this cartridge can run NROM+UNROM games)
  • Order in which you put values doesn't matter (you can write 7400+74138+7400 or 7400+7400+74138 to search for a cartridge that contains at least two 7400 chips and one 74138
  • Some chips (like PAL16*8) appear in cartridges as 16V8 or 16L8, so be sure to check both posibilities
  • Same goes for memories - type 27F080 to search for 32 pin memories, 27512 for 28 pin with two chip enables or MASKROM_1M_DIP28 for 28 pin with one chip enable
  • Same goes for mappers - some examples: AX5904(MMC1), AX5202P(MMC3), PT8154BM (9112MMC3), AX5208C(VRC4), 23C3662(VRC2)
  • Good news is that you can use wildcards, so 74139+*MMC3* will search for any cartrige that has at least one 74139 and MMC3 chip in any version
Mapper#
Original mapper#
PCB marks
Tags
Chips
Super Mario Bros 2 (J)
Typesingle
Mapper40
Original mapper
PCB marks921001
Tags:#fds #smb2j
Uploaded:2020-02-05 10:26:45

Elements:
NameValue
IC127512
IC26264
IC374138
IC474161
IC57400
IC67432
IC77400
IC874157
IC94020
CART1FAMICOM_CART

Chip signature:
27512+6264+74138+74161+7400+7432+7400+74157+4020

PCB top:

PCB bottom:

Shell top:
No photo

Shell bottom:
No photo
Screenshoots:

Extra info:
SMBJ2 ([mapper 40) a'ka 1990 Super Bros.4 - rev en

Finally got this rare SMB2J based on discrete chips (no PAL). It turned out to be [url=http://wiki.nesdev.com/w/index.php/INES_Mapper_040]mapper 40[/url]. I was wondering how did they wire all these chips to achieve that weird fixed banks. ([url=https://forums.nesdev.com/viewtopic.php?f=28&t=17108]I was able to do it using 2 chips less back in the days[/url]).

Funny how they used 2 NAND gates to make latch for IRQ assert/deassertion. And how the PRG/CHR address lines are shuffled.

PRG is identical to `Super Mario Bros. 4 (FDS Conversion)(Unl)[!]`, CHR differs in few bytes. And the difference is because of.. mario's outline:
[img]https://obrazki.elektroda.pl/2818807300_1580943774.png[/img]


[code]
$8000-$9fff: [........] - write acknowledges IRQs, clears and stop counter

$a000-$bfff: [........] - write starts counter (clocked by CPU cycles).
                          After 4096 cycles (~36 scanlines) IRQ is generated
						  
$e000-$ffff: [.....PPP] - set prg bank

    $6000 $8000 $a000 $c000 $e000
     %110  %100  %101   PPP  %111
	 
Bus conflicts: no
[/code]

[url=https://obrazki.elektroda.pl/3332972300_1580943483_org.jpg][img]https://obrazki.elektroda.pl/3332972300_1580943483_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/6815700400_1580978383_org.jpg][img]https://obrazki.elektroda.pl/6815700400_1580978383_thumb.jpg[/img][/url]  [url=https://obrazki.elektroda.pl/9444002200_1580943484_org.jpg][img]https://obrazki.elektroda.pl/9444002200_1580943484_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/6297947500_1580943485.png][img]https://obrazki.elektroda.pl/6297947500_1580943485_thumb.jpg[/img][/url] 

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