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Cart name
Notes for chip search:
  • Use "+" as delimeter for all fields (except "cart name", where space is used); if many values are entered, all of them must appear in the cartridge then; case is not sensitive
  • "Mapper" is the actual mapper used by this cartridge hardware (might not match the one at wiki.nesdev.com, as at the moment I was analyzing this cartridge, there was no mapper assigned to it, so I had to assign my own number for testing)
  • "Original mapper" is the mapper used by licensed version of this game (for multicarts, it refers to mapper of the inside games, so 0+2 means this cartridge can run NROM+UNROM games)
  • Order in which you put values doesn't matter (you can write 7400+74138+7400 or 7400+7400+74138 to search for a cartridge that contains at least two 7400 chips and one 74138
  • Some chips (like PAL16*8) appear in cartridges as 16V8 or 16L8, so be sure to check both posibilities
  • Same goes for memories - type 27F080 to search for 32 pin memories, 27512 for 28 pin with two chip enables or MASKROM_1M_DIP28 for 28 pin with one chip enable
  • Same goes for mappers - some examples: AX5904(MMC1), AX5202P(MMC3), PT8154BM (9112MMC3), AX5208C(VRC4), 23C3662(VRC2)
  • Good news is that you can use wildcards, so 74139+*MMC3* will search for any cartrige that has at least one 74139 and MMC3 chip in any version
Mapper#
Original mapper#
PCB marks
Tags
Chips
4 in 1 soccer
Typemulti
Mapper
Original mapper4
PCB marksN42
Tags:
Uploaded:2019-08-28 02:42:51

Elements:
NameValue
IC16264
IC2YD925-A(27F080)
IC3C5052-13(DIL40)
IC4YD925-B(27F080)
IC57402
IC64013
IC774125
C1?
C2100n
C3100n
CART1FAMICOM_CART
D1
D2
D3
G1CR2032
R11k

Chip signature:
6264+YD925-A(27F080)+C5052-13(DIL40)+YD925-B(27F080)+7402+4013+74125

PCB top:

PCB bottom:

Shell top:


Shell bottom:

Screenshoots:
No photo
Extra info:
This reset-baset cartridge consists of 4 games and uses mysterious DIP40 "C5052-13" chip (and a battery backup which is rare for pirate games). 
[url=https://obrazki.elektroda.pl/7320428500_1567071672.jpg][img]https://obrazki.elektroda.pl/7320428500_1567071672_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/8122479100_1567071674.jpg][img]https://obrazki.elektroda.pl/8122479100_1567071674_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/7153343200_1567071675.jpg][img]https://obrazki.elektroda.pl/7153343200_1567071675_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/9593876200_1567071676.jpg][img]https://obrazki.elektroda.pl/9593876200_1567071676_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/7551899400_1567071728.png][img]https://obrazki.elektroda.pl/7551899400_1567071728_thumb.jpg[/img][/url] 

At first I thought it is MMC3 clone, but when I dumped the games, one of them turned out to be MMC1:
[code]
Downtown - Nekketsu Koushin Kyoku - Soreyuke Dai Undoukai (J)     | MMC3
Downtown Special - Kunio Kun no Jidaigeki Dayo Zenin Shuugou! (J) | MMC3 + WRAM + battery backup
Nekketsu Kakutou Densetsu (J)                                     | MMC3
Nekketsu Koukou Dodgeball Bu (J)                                  | MMC1
[/code]

Depending on the pin 2, it switches its functionality between MMC1 (disconnected) and MMC3 (VCC).
The connection was unclear to me:
* they used additional 74125 buffer just to invert the signal (three other 74125's gates are unused), but there was still one 7402 NOR unused that could be utilized for that purpose.
* the output of 74125 is not pulled down which causes the signal to be at 2.5V when in MMC1 mode
* CPU-A1 and CPU-A12 are wired into mapper but neither MMC1 nor MMC3 needs it 
When in MMC1 mode, PRG A18 is at GND and so does CHR A17.
[img]https://obrazki.elektroda.pl/8424402400_1567071050.png[/img]

[code]
             .--\/--. 
      +5V -- |01  40| <- CPU A0
     mode -> |02  39| <- CPU A1
  PRG A13 <- |03  38| <- M2
  PRG A14 <- |04  37| <- CPU A12
  PRG A15 <- |05  36| <- CPU A13
  PRG A16 <- |06  35| <- CPU A14
  PRG A17 <- |07  34| <- CPU D4
  PRG A18 <- |08  33| <- CPU D5
  PRG /CE <- |09  32| <- CPU /ROMSEL
 WRAM +CE <- |10  31| <- CPU D6
  CHR A10 <- |11  30| <- CPU D7
  CHR A11 <- |12  29| <- CPU D0
  CHR A12 <- |13  28| <- CPU R/!W
  CHR A13 <- |14  27| -> CIRAM A10
  CHR A14 <- |15  26| <- CPU D1
  CHR A15 <- |16  25| <- CPU D2
  CHR A16 <- |17  24| <- CPU D3
  CHR A17 <- |18  23| -> PPU A12
     /IRQ <- |19  22| -> PPU A11
      GND -- |20  21| -> PPU A10
             `------' 
             C5052-13 
[/code]

Then I tried pulling pin 2 to ground (using 100R resistor for safety) and it seems to go into third mode. I thought it might be VRC2 or VRC4.
* Writing $00/$01/$02/$03 to $9000/$9001/$9002/$9003 switches between V and H mirroring (so it seemed to be VRC2 as VRC4 has also 0/1 mode), but
* Writing to any of $X00Y where X=8/9/a/b/c/d/e/f and Y=0/1/2/3 does not seem to alter PRG bank
* Writing to $b000/b001 (and $b002/$b003) manipulates CHR bank at $400.
* When in MMC3/MMC1 mode - WRAM at $6000-$7fff is enabled and when in this semi-VRC mode, it is disabled
Either the VRC2 mode is broken, or this is not VRC chip.

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