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  • "Mapper" is the actual mapper used by this cartridge hardware (might not match the one at wiki.nesdev.com, as at the moment I was analyzing this cartridge, there was no mapper assigned to it, so I had to assign my own number for testing)
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Mapper#
Original mapper#
PCB marks
Tags
Chips
Gyruss
Typesingle
MapperUNL-KS7057
Original mapper
PCB marksKS-7057
Tags:#fds #kaiser
Uploaded:2018-04-14 11:41:33

Elements:
NameValue
IC127512
IC107432
IC274157
IC3KS204-VRC2
IC474139
IC57400
IC66264A
IC77474
IC87400
IC974157
C1?
C2-
C3-
CART1FAMICOM_CART
R11.5k
R2100

Chip signature:
27512+7432+74157+KS204-VRC2+74139+7400+6264A+7474+7400+74157

PCB top:

PCB bottom:

Shell top:
No photo

Shell bottom:
No photo
Screenshoots:

Extra info:
	
Gyruss (FDS Conversion) (Kaiser KS-7057)

After finishing my analysis of [url=http://forums.nesdev.com/viewtopic.php?f=9&t=19251]Kaiser KS-7037 Metroid[/url], Gyruss KS-7057 was the last one of that series that bothered my mind.

The PCB is desribed as [url=https://wiki.nesdev.com/w/index.php/NES_2.0_Mapper_302]Mapper 302[/url]. However, the description does not match the hardware - KS204 is MMC3 predecessor with 4*6 bit CHR regs, 2*5 bit CHR regs and 2*4 bit PRG regs, while this 128KiB game using 2KiB banks needs 8*6 regs + mirroring and except one 7474 there are no more latches in that PCB.

I gave my best to trace the PCB to follow the description (I dont physically have the PCB).

* Mirroring register is done using 7474 and it is placed at $8000-$9fff (mask $E000) [.......M], 0=H, 1=V (opposite what wiki says)
* KS204 is wired in a way so that it controls PRG banks using its CHR registers (KS204_PPU_A12..A10 <= CPU_A13..A10)
* I don't think I quite follow what is going with the KS204's D5..D0 and A14/A13/A0:
[img]https://obrazki.elektroda.pl/5381322800_1568977797.png[/img]
  - IC10B from logical view point is doing nothing, but electrically it adds delay to rising/falling edge of M2
  - if so, on the rising edge of M2, KS204 sees:
		pin3 = CPU-A14,
		pin4 = CPU-A13,
		pin5 = CPU-A12,
		pin6 = CPU-A1,
	and on the falling edge:
		pin3 = CPU-D3
		pin4 = CPU-D2
		pin5 = CPU-D1
		pin6 = CPU-D0
  - KS204 pin 9 is wired to CPU A0,
  - KS204 pin 8 is wired to CPU D4 (according to mapper description, D4 shouldn't be taken into account at all)
  This makes me think that KS204 despite similar pinout is not behaving the same like in [url=http://forums.nesdev.com/viewtopic.php?f=9&t=19251]Kaiser KS-7037 Metroid[/url] PCB (is it some programmable chip?)

* PRG memory map is 
[code]			 
      | /RM CPU CPU CPU CPU | PRG PRG PRG PRG PRG PRG | comment
 ADR  | SEL A14 A13 A12 A11 | A16 A15 A14 A13 A12 A11 |
$6000 |  1   1   1   0   0  |  E   E   e   e   e   e  |
$6800 |  1   1   1   0   1  |  F   F   f   f   f   f  |
$7000 |  1   1   1   1   0  |  G   G   g   g   g   g  |
$7800 |  1   1   1   1   1  |  H   H   h   h   h   h  |
$8000 |  0   0   0   0   0  |  A   A   a   a   a   a  |
$8800 |  0   0   0   0   1  |  B   B   b   b   b   b  |
$9000 |  0   0   0   1   0  |  C   C   c   c   c   c  |
$9800 |  0   0   0   1   1  |  D   D   d   d   d   d  |
$a000 |  0   0   1   0   0  |  1   1   0   1   0   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$a800 |  0   0   1   0   1  |  1   1   0   1   0   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$b000 |  0   0   1   1   0  |  1   1   0   1   1   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$b800 |  0   0   1   1   1  |  1   1   0   1   1   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$c000 |  0   1   0   0   0  |  1   1   1   0   0   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$c800 |  0   1   0   0   1  |  1   1   1   0   0   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$d000 |  0   1   0   1   0  |  1   1   1   0   1   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$d800 |  0   1   0   1   1  |  1   1   1   0   1   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$e000 |  0   1   1   0   0  |  1   1   1   1   0   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$e800 |  0   1   1   0   1  |  1   1   1   1   0   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$f000 |  0   1   1   1   0  |  1   1   1   1   1   0  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11
$f800 |  0   1   1   1   1  |  1   1   1   1   1   1  |  PRG_A16 = 1, PRG_A15 = 1, PRG_A14..A11 = CPU_A14..A11

Internal registers:
p3 p4 p5 p6 p9 |
 0  1  1  0  0 | $b000 [....aaaa]
 0  1  1  0  1 | $b001 [......AA]
 0  1  1  1  0 | $b002 [....bbbb]
 0  1  1  1  1 | $b003 [......BB]
 1  0  0  0  0 | $c000 [....cccc]
 1  0  0  0  1 | $c001 [......CC]
 1  0  0  1  0 | $c002 [....dddd]
 1  0  0  1  1 | $c003 [......DD]
 1  0  1  0  0 | $d000 [....eeee]
 1  0  1  0  1 | $d001 [......EE]
 1  0  1  1  0 | $d002 [....ffff]
 1  0  1  1  1 | $d003 [......FF]
 1  1  0  0  0 | $e000 [....gggg]
 1  1  0  0  1 | $e001 [......GG]
 1  1  0  1  0 | $e002 [....hhhh]
 1  1  0  1  1 | $e003 [......HH]

[/code]

b000

[url=https://obrazki.elektroda.pl/3972340600_1568978342.png][img]https://obrazki.elektroda.pl/3972340600_1568978342_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/8497799400_1568978357.png][img]https://obrazki.elektroda.pl/8497799400_1568978357_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/8198805600_1568978359.png][img]https://obrazki.elektroda.pl/8198805600_1568978359_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/1899138900_1568978404.jpg][img]https://obrazki.elektroda.pl/1899138900_1568978404_thumb.jpg[/img][/url] 

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