Unique visits: 7438 Can you help getting more info about those carts? |
|
Name | Value |
---|---|
IC1 | 27256 |
IC2 | 27512 |
IC3 | 27512 |
IC4 | 6264 |
IC5 | 16L8 |
CART1 | FAMICOM_CART |
http://famiclone.com/forum/main-forum/28-green-beret d:\!EMU\fceultra-code-3320-fceu-trunk\src\boards\ac-08.cpp Green Beret FDS port No physical access to the cartridge so can't confirm if it is Kaiser or Whirlwind Manu version, but both use the same mapper UNIF AC-08. [code] $8001 ~[...PPPP.] (mask=$E001) |||| |+++- PRG bank at $6000 +---- PRG chip select: 0 = PRG1 = IC2 1 = PRG2 = IC3 $6000 $8000 $a000 $c000 $e000 ----- ----- ----- ----- ----- Bank $8001 0000 0001 0010 0011 Chip PRG1/2 PRG3 PRG3 PRG3 PRG3 [/code] * [url=https://github.com/TASVideos/fceux/blob/master/src/boards/ac-08.cpp]FCEUX source[/url] claims that UNIF AC-08 mapper is also used for Castlevania (FDS port?) but with shifted bits and selectable mirroring, while this one does not have capability of mirroring select. * [url=http://wiki.nesdev.com/w/index.php/UNIF_to_NES_2.0_Mapping]Wiki[/url] claims that AC-08 is mapped do 42.0, which is not compatible. [url=https://obrazki.elektroda.pl/7630166600_1589621437.jpg][img]https://obrazki.elektroda.pl/7630166600_1589621437_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/7966557900_1589621439.jpg][img]https://obrazki.elektroda.pl/7966557900_1589621439_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/6053941600_1589621442.png][img]https://obrazki.elektroda.pl/6053941600_1589621442_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/6422551100_1589621497.jpg][img]https://obrazki.elektroda.pl/6422551100_1589621497_thumb.jpg[/img][/url] [url=https://obrazki.elektroda.pl/9575855700_1589621541.png][img]https://obrazki.elektroda.pl/9575855700_1589621541_thumb.jpg[/img][/url] [code] PAL pinout: .--v--. M2 -> |01 20| -- +5V CPU_nROMSEL -> |02 19| CPU_A14 -> |03 18| -> PRG_A13 CPU_A13 -> |04 17| -> PRG_A14 CPU_RnW -> |05 16| -> PRG_A15 CPU_D4 -> |06 15| -> PRG2_nOE CPU_D3 -> |07 14| -> PRG1_nOE CPU_D2 -> |08 13| -> PRG3_nOE CPU_D1 -> |09 12| -> PRG12_nCE GND -- |10 11| <- CPU_A0 '-----' Expected PAL equations: PRG_A13 <= CPU_D1 when M2='1' & CPU_nROMSEL='0' and CPU_A14='0' and CPU_A13='0' and CPU_A0='1' and CPU_RnW='0' --latch PRG_A14 <= CPU_D2 when M2='1' and CPU_nROMSEL='0' and CPU_A14='0' and CPU_A13='0' and CPU_A0='1' and CPU_RnW='0' --latch PRG_A15 <= CPU_D3 when M2='1' and CPU_nROMSEL='0' and CPU_A14='0' and CPU_A13='0' and CPU_A0='1' and CPU_RnW='0' --latch PRG2_nOE <= CPU_D4 when M2='1' and CPU_nROMSEL='0' and CPU_A14='0' and CPU_A13='0' and CPU_A0='1' and CPU_RnW='0' --latch PRG1_nOE <= not PRG2_nOE --or either latches not CPU_D4 like above, but functionally equivalent PRG3_nOE <= '0' when M2='1' and CPU_nROMSEL='1' and CPU_A14='1' and CPU_A13='1' and CPU_RnW='1' else 0 PRG12_nCE <= '0' when CPU_nROMSEL='0' and CPU_RnW='1' else 0 [/code]
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