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Type single Mapper 268 Original mapper 4 PCB marks 890418 Tags: #smb3 #big Uploaded: 2022-11-28 01:16:08

This board, made entirely from discrete chips, is used by Super Mario Bros 3 bootleg. The game was modified (with copyright information cut out) and ported from MMC3.
[[File:SMB3_m106_components.jpg|thumb]] [[File:SMB3_m106_top.jpg|thumb]] [[File:SMB3_m106_bottom.jpg|thumb]] [[File:SMB3_m106_schematics.png|thumb]] 

==Memory map==
*PRG-ROM: 2x128 KiB
*CHR-ROM: 128 KiB
*PRG-RAM: 8 KiB


* CPU $6000-$7FFF: 8 KB PRG RAM bank
* CPU $8000-$9FFF: 8 KB switchable PRG ROM bank0
* CPU $A000-$BFFF: 8 KB switchable PRG ROM bank1
* CPU $C000-$DFFF: 8 KB switchable PRG ROM bank2
* CPU $E000-$FFFF: 8 KB switchable PRG ROM bank3


* PPU $0000-$03FF  1 KB switchable CHR bank
* PPU $0400-$07FF  1 KB switchable CHR bank
* PPU $0800-$0BFF  1 KB switchable CHR bank
* PPU $0C00-$0FFF  1 KB switchable CHR bank
* PPU $1000-$13FF  1 KB switchable CHR bank
* PPU $1400-$17FF  1 KB switchable CHR bank
* PPU $1800-$1BFF  1 KB switchable CHR bank
* PPU $1C00-$1FFF  1 KB switchable CHR bank

Subject to bus conflicts: no

==Registers==
There are 16 registers at $8000-$800f. Only A3-A0 is taken into account (mask $800F)

===CHR banking ($8000-$8007) ===
 [.CCC CCC0] $8000
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $0000-$03ff

 [.CCC CCC1] $8001
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $0400-$07ff

 [.CCC CCC0] $8002
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $0800-$0bff

 [.CCC CCC1] $8003
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $0c00-$0fff

 [.CCC CCCC] $8004
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $1000-$13ff

 [.CCC CCCC] $8005
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $1400-$17ff

 [.CCC CCCC] $8006
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $1800-$1bff

 [.CCC CCCC] $8007
   ||| ||||
   +++-++++- 1 kB CHR ROM bank at $1c00-$1fff

===PRG banking ($8008-$800b)===
 [.... PPPP] $8008
       ||||
       ++++- 8 kB PRG ROM bank at $8000-$9fff (from ROM 5602)

 [...R PPPP] $8009
     | ||||
     | ++++- 8 kB PRG ROM bank at $a000-$bfff
     +------ ROM select at $a000-$bfff (0: 5601, 1: 5602)

 [...R PPPP] $800a
     | ||||
     | ++++- 8 kB PRG ROM bank at $c000-$dfff
     +------ ROM select at $c000-$dfff (0: 5601, 1: 5602)

 [.... PPPP] $800b
       ||||
       ++++- 8 kB PRG ROM bank at $e000-$ffff (from ROM 5602)

Note: if you combine 128K ROM 5601 with 128K ROM 5602 into one 256K ROM, add 16 to $8008/$800b and treat RPPPP from $8009/$800a as 5-bit bank number.

===Mirroring ($800c)===
 [.... ...M] $800c
          |
          +- mirroring (0: V, 1: H)

===Counter and interrupts ($800d-$800f)===
There in one 16 bit counter, which increments at end of each CPU cycle (on falling edge of M2). If it wraps from 2^16 - 1 to 0, interrupt (when enabled) is fired and counter is stopped.

 [.... ....] $800d - writing any value sets counter to 0, disables interrupts,
                     acknowledges pending interrupt and starts counter.

 [DDDD DDDD] $800e
  |||| ||||
  ++++-++++- set low byte of counter to this value

 [DDDD DDDD] $800f
  |||| ||||
  ++++-++++- set high byte of counter to this value, enable interrupts, acknowledges pending interrupt and start counter

==Trivia==
* FCEUX implementation is not 100% accurate with hardware. Here are differences:
** none of the registers is cleared or initialized to known value at startup,
** CHR registers does not take into account bit 7,
** writing to $800d does not stop counter, but starts it and interrupt firing is disabled.
* This version of SMB3 works only in NTSC/Dendy mode.

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