Unique visits: 8968 Can you help getting more info about those carts?

Type single Mapper 21 Original mapper 21 PCB marks P-4073 PP-43KII Tags: Uploaded: 2021-11-12 07:26:37

I analyzed your cartridge and this cartridge is very interesting

1) The wires and cut traces at the bottom are  because they used 128kB DIP28 instead of DIP32 CHR-ROM (which has only one input enable). The jumpers on the attached schematic should explain it all.

2) The PT8155 is indeed VRC4 but WITHOUT CHR-A17 and PRG-A17. No idea if those two pins are not present because it is broken or manufacftured that way or reused inside chip for other purposes. The goal of all those chips is to add missing functionality of CHR-A17 and PRG-A17 (CHR-A17 is in fact not used in this PCB because Wai Wai has only 128kB of CHR-RAM and so the track is cut off)

3) VRC4 has 8 CHR registers (https://wiki.nesdev.org/w/index.php?title=VRC2_and_VRC4#CHR_Select_0_low.28.24B000.29.2C_high.28.24B001.29)
High nibbles lie at $B002, B006, C002, C006, D002, D006, E002, E006). The purpose of 74259 + 74151 is to latch CPU-D3 and mux it into CHR-A17

4) VRC4 has 2 PRG registers. Two 74*74s (IC5B, IC5A) latch those bits as well as the PRG SWAP MODE BIT (IC6A) and those 3 bits are fed into PAL, which decides which bit should be applied as PRG-A17

5) PAL is pure combinational, the equations can be easily deduced from the above description.

6) If you could confirm just if
* IC4.11 connects to IC5.9 or IC5.8?
* IC4.9 connects to IC5.5 or IC5.6?

7) The reason why graphic is garbled is because your dump of CHR is invalid (first and second half of this 128kB ROM that you sent is identical)


-----------------CHR BANKING---------------------------------
         +----------------CPU A14  
         | +--------------CPU A13
         | |+-------------CPU A12
         | ||         +---CPU A2
         | ||         |+--CPU A1
         | ||         ||         PPU  PPU  PPU
         | ||         ||         A12  A11  A10
         | ||         ||         (S2) (S1) (S0)
$B002 = 10 11*********01*   ->    0    0    0
$B006 = 10 11*********11*   ->    0    0    1
$C002 = 11 00*********01*   ->    0    1    0
$C006 = 11 00*********11*   ->    0    1    1
$D002 = 11 01*********01*   ->    1    0    0
$D006 = 11 01*********11*   ->    1    0    1
$E002 = 11 10*********01*   ->    1    1    0
$E006 = 11 10*********11*   ->    1    1    1

74259-S0 <= CPU A2

74259-S1 <= '1' when (CPU_A13 = '0' and CPU_A12 = '0') or (CPU_A13 = '1' and CPU_A12 = '0') else '0'

74259-S2 <= '1' when (CPU_A13 = '0' and CPU_A12 = '1') or (CPU_A13 = '1' and CPU_A12 = '0') else '0'

74259-nG <= '0' when CPU_nROMSEL = '0' and CPU_RnW = '0' and CPU_A14 = '0' and CPU_A13 = '1' and CPU_A12 = '1' and CPU_A1 = '1' else
            '0' when CPU_nROMSEL = '0' and CPU_RnW = '0  and CPU_A14 = '1' and CPU_A13 = '0'                   and CPU_A1 = '1' else
            '0' when CPU_nROMSEL = '0' and CPU_RnW = '0  and CPU_A14 = '1' and CPU_A13 = '1' and CPU_A12 = '0' and CPU_A1 = '1' else
           '1'
           
-----------------PRG BANKING---------------------

                              +----- CPU A14
                              |+---- CPU A13
                              ||+--- CPU A12
                              |||
$8000/$8004/$8008/$800C      1000************
$A000/$A004/$A008/$A00C      1010************

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