https://cah4e3.shedevr.org.ru/bonza.php
Chips used:
ЭКФ1533ИЕ10=74161
ЭКФ1533ЛП8=74125
ЭКФ1533ЛИ1=7408
ЭКФ1533ЛН2=7405
ЭКФ1533ЛА4=7410
ЭКФ1533ИД7=74138
ЭКФ1533ТМ2=7474
Mirroring = H
SIM1 = small card on top side that contains backup of credits and some demos (?)
SIM2 = big card on bottom side that contains credits
=============================== $5000 (W) ===============================
At the beginning of CPU cycle, SIM1's & SIM2's CCVCC will be set to +5V
76543210
[CcrdD.cd] @
||||| |+-- value to be written to SIM2 CCIO (when $5000.3 == 1)
||||| +--- SIM2 CCCLK latch
||||+----- SIM1/2 CCCIO data direction (0=from card, 1=to card)
|||+------ value to be written to SIM1 CCIO (when $5000.3 == 1)
||+------- SIM1 CCRST latch
|+-------- SIM1 CCCLK latch
+--------- what drives SIM2 CCCLK: 0=$5000.1, 1=$5000.1 AND /M2
=============================== $5000 (R) ===============================
At the beginning of CPU cycle, SIM1's & SIM2's CCVCC will be set to +5V
76543210
[jd.....d] @
|| +- value from SIM2 CCIO (when $5000.3 == 1)
|+------- value from SIM1 CCIO (when $5000.3 == 1)
+-------- value from SIM2 detector (when $5000.3 == 1): 0=card present, 1=no card
=============================== $6000 (R/W) ===============================
At the beginning of CPU cycle, SIM2's CCVCC will be set to 0V
=============================== $7000 (R/W) ===============================
At the beginning of CPU cycle, SIM1's CCVCC will be set to 0V
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